We’ve recently designed a board with a Xilinx FPGA on it. One of the first test projects is to run a cpu core in the FPGA. Since I am familiar with the Microchip PIC series of microcontrollers, why not see if a FPGA can work like a PIC. Instead of trying to write my own PIC cpu core in VHDL/Verilog, I tested cores from Opencores and Silicore. Opencores has several opensource PIC cores available for download. The one I was able to get to work in actual hardware is risc16f84 written by John Clayton. He has several versions but the one used is risc16f84_clk2x.v. To begin, download his b13c_environment.zip demo file. This is his risc16f84_clk2x.v processor with hardware debugging, serial port and LCD panel driver.
Xilinx ISE6.1sp3 with XST was used to compile the verilog source for a XC2S100 Spartan2 FPGA. The top level hierarchy is called “top.v” and the rest of the source files was then added to the project. After synthesizing, I quickly found that it wouldn’t fit in my 100K Spartan chip. John had targeted his demo for a 200K gate FPGA. Since I don’t have a LCD panel, the blockrams and driver code associated with the LCD in “top.v” was removed. The project was synthesized again and this is the device utilization summary:
Selected Device : 2s100tq144-6
Number of Slices: 827 out of 1200 68%
Number of Slice Flip Flops: 591 out of 2400 24%
Number of 4 input LUTs: 1513 out of 2400 63%
Number of bonded IOBs: 94 out of 96 97%
Number of TBUFs: 128 out of 1200 10%
Number of BRAMs: 5 out of 10 50%
Number of GCLKs: 2 out of 4 50%
827 slices and 5 BRAMS, it fit! The next step is to create a constraint file and assign some FPGA pins for the clock, serial port and port I/O. A Maxim232 serial chip was wired to the FPGA and connected to COM2 on the PC. The project files were again synthesized, implemented and the bit file was downloaded to the FPGA using IMPACT. I started up a terminal program set for COM2, hit the enter key a couple of times and the FPGA responded back, it worked!
John has written a perl script, srec_to_rs232.pl, that will convert compiled PIC HEX files to formatted ascii text for downloading to the FPGA. I wrote a small program using CCS PCW C compiler to toggle some port i/o pins. After converting the HEX file with srec_to_rs232.pl script, I used the terminal program’s “Send Ascii” file transfer feature to download it to the FPGA’s dual port ram. After resetting the cpu, the I/O pins toggled on the oscilloscope screen. The debugging environment works great. There are commands to read/write memory locations and view the registers while programs are running. There is also the ability to single step with breakpoints for debugging purposes.
The risc16f84_clk2x.v processor doesn’t have some of the standard features found in a real 16F84 chip, no 8bit timer, no watchdog and only 1 interrupt source. Since the FPGA has some extra slices available, I made my own 8 and 32 bit timers, 8 bit PWM, added 32 more I/O pins and dedicated quadrature decoder counters. A watchdog and more interrupt sources can be added if needed. The FPGA ran without problems with a 40Mhz clock, the fastest I have available to test. This core uses 2 clocks per instruction which means it runs approximately 4 times faster (20MIP) than a equivalent 20Mhz PIC16F84 chip (5MIP). You can call this a super F84 chip. Several other C test programs were written and none had any problems running on the FPGA.
2/15/2005 Update: The Silicore website seems to be unavailable so I have mirrored the VHDL files here.
The SLC1657 is a VHDL core that is software compatible to the Microchip PIC16C57 microcontroller. Silicore has released the VHDL code under the GNU Lesser General Public License (LGPL), a open source license. This is a 1 clock cycle per instruction implementation so it runs very fast. This core was easy to get working in Xilinx ISE since they provide a detailed instructions manual on how to create the blockrams and configure the synthesis software. Silicore also provides a example top level hierarchy “xsp2eval.vhd” that can be used to test the core out.
Downloading programs to the SLC1657 is different than the risc16f84 core. Silicore implements a “Serial emulation rom interface” that is connected to the PC parallel port with 4 wires. Using a special downloader.exe program provided, HEX files can be sent directly to the FPGA. This is much faster than using a serial COM port and quicker than my hardware PIC programmer.
I wrote a number of C test programs in CCS and Hi-Tech C and they all ran as expected. There are some minor differences between the SLC1657 and the real chip which are fully documented in the manual. The 8bit timer TMR0 worked flawlessly. A 20Mhz clock was used to test the core. Xilinx synthesis reports a maximum frequency of 31Mhz for the Spartan FPGA.
This is our custom FPGA board that was used to test the PIC cores. It is a 4 layer board with a PIC18F458, Maxim A/D and D/A, and serial port located on the left side. The Xilinx Spartan2 XC2S100 FPGA is on the right.